(9/9)ECTC2026での発表を解説　先端半導体パッケージング・実装技術の研究開発動向

１．ECTCの紹介と最近の研究動向、および用語の説明
　1.1 ECTCの発表件数の推移や国別／研究機関別投稿状況
　1.2 先端半導体パッケージングの分類や動向
　1.3 ハイブリッド接合の概要
　1.4 Co-Packaged Optics (CPO)の概要

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２．ハイブリッド接合と光電融合以外の注目論文 10件

Session 1: Enabling Fan-In and Fan-Out Wafer/Panel Level Packaging Technology
・Paper 1. A Novel 600mm Panel Interposer with 300mm Panel Assembly Approach for Advanced Packaging 　　
　　　　　 Solution in HPC and AI Applications (ASE)

Session 7: Heterogeneous Integration: The New Horizons
・Paper 1. Scaling the EMIB-T Advanced Packaging Technology to Address the Future HPC/AI Demand (Intel)

Session 10: Reliability of Large Body High Performance Computing and AI Packaging Solutions
・Paper 3. The First Report of Si Bridge Type 2.5D Package Reliability for Automotive Applications
(Socionext;, Renesas Electronics & MIRISE)

Session 13: Advances in Thermal Design and Characterization
・Paper 1. Process Development and Thermal Characterization of Micropillar Direct-to-Silicon Liquid Cooling
Solution on CoWoS-R Platform (TSMC)

Session 14: RDL and Fan-Out Interconnections
・Paper 2. Panel CMP Co-Planarization of Heterogeneous Interfaces for Damascene Organic RDL Interposers (L/S = 2/2μm)
(Resonac)

Session 16: Assembly and Manufacturing: 3D Stacking and Thermal Solutions
・Paper 2. First Demonstration of μBump-Based Massive Orthogonal Stacking Assembly IC (MOSAIC) Cube for
SoC-DRAM Direct (The University of Tokyo and Tohoku University)

Session 19: Substrate Core Innovations: Glass, Ceramic, and Silicon
・Paper 2. Glass Core Substrates Next Generation Advanced Packaging Platform for AI and HPC (Intel)

Session 29: Innovation in Metallization, Alignment, Additive Manufacturing, and Low Temperature
Interconnection
・Paper 5. Metallization Challenges: Conformable Deposition for Super High-Aspect Ratio (> 100) Fine TGV and Cu
Pillar Embedment for 1mm-Deep Fat TGV (Tohoku University, T-Micro & Micro Technology)

Session 32: Solder and Through Via Interconnections: Material & Process Innovations
・Paper 7. Chemically-Tailored Cu Electroplating and Contactless Isostatic-Pressure Annealing of 1mm-Thick Full
Glass Wafer Cu Through-Glass Vias (Cu-TGVs) (Tohoku University, T-Micro & JCU)

Session 39: Interactive Presentations Bonding Processes and Analysis in Next Generation Interconnects
・Paper 23. Reliable and Cost-Effective Fabrication of Low-Resistive and Void-Free Through-Glass Vias Using a
Reduction Gas-Generating Sinterable Cu Paste (Tohoku University, T-Micro & Daicel)

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３．ハイブリッド接合 63件

Session 3: Advances in Low Temperature Hybrid Bonding
　・Paper 1. Hybrid Bonding With Ultra-Low Temperature Annealing: Morphological and Electrical Validations
　　　　　　 (Univ. Grenoble Alpes & CEA-LETI)
　・Paper 2. Pressure-less Cu/Polymer Hybrid Bonding at Low Temperature and Fine Pitch Using a Novel Polymer
Adhesive with Precisely Controlled Composition (Mitsui Chemicals & ASE)
　・Paper 3. Reliable Low-Temperature ( 250・C) Cu/Dielectric Hybrid Bonding for High-Bandwidth Memory (HBM)
Stack Integration (IME)
　・Paper 4. Low-Temperature Chip Scale Cu-Cu Hybrid Bonding by Electroless Ag Passivation
(National Taiwan University)
　・Paper 5. Enabling Low-Temperature Fine-Pitch Hybrid Bonding: Role of Nanocrystalline Copper Microstructures
and Pre-Bond SurfaceTreatments (ST Microelectronics & Univ Grenoble Alpes)
　・Paper 6. Polymer Fillet Integration to Improve Die Thinning and Inter-die Gap Fill Yield and Reliability in Die-to
Wafer Hybrid Bonding (IBM)

Session 4: Breakthrough in Pitch Scaling With Advanced Bonding Technology
　・Paper 1. 100-nm-level Post-Bond Accuracy and High-Yield Die-to-Wafer Hybrid Bonding System Using
Non-Contact Die Transfer
(Toray Engineering, Yokohama National University, The University of Tsukuba & Tohoku University)
　・Paper 2. A Study of Chiplet Distortion in Chip-to-Wafer (C2W) Hybrid Bonding (Intel)
　・Paper 4. Assembly Process Optimization to Reduce Particle-Induced and non-Particle-Induced Voids in Chip-to-
Wafer Hybrid Bonding (IME, Besi & Applied Materials Singapore)

Session 8: Die-to-Wafer Hybrid Bonding: Current Advancements and Future Directions
　・Paper 1. Ultra-Fine 1.4-μm Pitch Face-to-Back Chip-on-Wafer Cu-Cu Hybrid Bonding for the
Chip-on-Wafer-on-Wafer Integration (Sony)
　・Paper 2. Process Optimization for Chip to Wafer Hybrid Bonding Using Inter Die Gap Fill Integration
Approach (IME)
　・Paper 3. Characterization of Bonding Behavior and Void Formation in Chip-on-Wafer Hybrid Bonding (ASE)
　・Paper 4. Inverse Hybrid Bonding at 5 μm Pitch for High-Density Heterogeneous Integration (Georgia Tech)
　・Paper 5. Development of Particle Robust Micro-Scale Interconnect by Cured-Polymer and Solder (MICS)
Technology Down to 3 μm Pitch (Rapidus)
　・Paper 7. Next-Generation Optical-Electrical Co-Design Interconnect Using Low-Temperature Hybrid Bonding
Technology (National Yang Ming Chiao Tung University, Tokyo Electron America, & TOK)
※ 4.光電融合(Co-PKG)でも言及します

Session 10: Reliability of Large Body High Performance Computing and AI Packaging Solutions
　・Paper 7. Predictive Reliability Modeling of Hybrid Bonding Through Warpage and Interfacial Defect Correlation
(University of Florida)

Session 17: Digital Twin and AI in Advanced Packaging and Interconnect Security
　・Paper 4. Fabrication and Experimental Characterization of Embedded Multi-Terminal Capacitors With Ultra Low
Parasitics for Integrated Vertical Power Delivery (Pennsylvania State University)

Session 18: Hybrid Bonding: Advanced Processing and Modeling
　・Paper 3. Effects of Chip Geometry and Bonding Initiation Point on Bonding Distortion in Die-to-Wafer Hybrid
Bonding (Sony)
　・Paper 4. First Demonstration of 450nm Pitch Cu-Cu Hybrid Bonding with 98% Yield Across 20M Interconnects
for Ultra-Dense 3D Integration (Applied Materials)
　・Paper 7. Fine-pitch Cu-Cu Hybrid Bonding Using Electroless deposited (111) Nanotwinned Cu
(National Taiwan University)

Session 20: Performance Analysis and Metrology of High-Bandwidth Electrical and Optical Interconnects
　・Paper 3. Novel Metrology For Experimentally Visualizing Cu-Cu Bonding Induced Thermal Stress
(Purdue University)

Session 26: Advanced Wafer-to-Wafer Hybrid Bonding
　・Paper 2. Reducing Wafer-to-Wafer Bonding Misalignment to Enable 140nm Pitch Hybrid Bonding
(Tokyo Electron America & Tokyo Electron Kyushu)
　・Paper 3. Wafer-to-Wafer Hybrid Bonding Technology with 200nm Interconnect Pitch (imec)
　・Paper 5. Process Integration for 300nm Pitch Hybrid Bonding with SiCN: 50nm Overlay, Fine-Grain Cu
Metallurgy, and Reliability Assessment (Applied Materials & EV Group)
　・Paper 6. Synchrotron-Based Characterization of Cu/SiCN Pretreatment for Hybrid Bonding via Ozone/Ethylene
Radical Activation (Tohoku University & MEIDEN NANOPROCESS INNOVATIONS)

Session 31: 3D Integration, TSV, and Hybrid Bonding Innovations
　・Paper 1. Die-To-Wafer Hybrid Bonding Technology Down to 1μm Pitch for Multi-Die Stacking Integration
　　　　　 (CEA-LETI)
　・Paper 2. Enabling Scalable Die-to-Wafer Hybrid Bonding Through Die Distortion Correction and Grid
Measurement (ASML)
　・Paper 3. Reworkable Die-to-Wafer Hybrid Bonding Process (Adeia)
　・Paper 4. Enabling Beyond-16-Layer 3D Stacking with Ultra-Thin Die Hybrid Bonding with Integrated Bonder
(Applied Materials)
　・Paper 7. Enabling Ultra Low Temperature Hybrid Bonding for D2W Scaling (Intel)

Session 33: Emerging Materials and Interconnect Technologies for Advanced Packaging
　・Paper 1. Optical RDL Interposer Technology Using Polymeric Hybrid Bonding and Waveguide for Integrated CPO
(Sumitomo Bakelite & Tohoku University)
※ 4.光電融合(Co-PKG)でも言及します

Session 35: Reliability of Advanced Automotive, AI, and Interconnect Packaging Solutions
　・Paper 5. Dependence of Leakage Current Characteristics on Bonding Dielectrics in Fine-Pitch Hybrid Cu Bonding
(Seoul National University)
　・Paper 7. Reliability Evaluation of 10-Second Cu/Polymer Hybrid Bonding for Next-Generation 3D Integration
(National Yang Ming Chiao Tung University)

Session 37: Interactive Presentations
Thermo-Mechanical Stress and Reliability Analysis for Materials in Future Packaging
　・Paper 7. Thermal Behavior of Hybrid Bonding Interfaces in Advanced Packaging Technologies (Intel)
　・Paper 10. Stress Analysis of Cu-Cu Hybrid Bonding Interface Under Thermal Loading
(Harbin Institute of Technology)

Session 38: Interactive Presentations
Photonics, mmWave Applications, and Emerging Technologies
　・Paper 27. Ultra High Resolution Micro-LED Display Enablement at 300mm Using W2W Hybrid Bonding for AI
and AR Applications (Applied Materials)

Session 39: Interactive Presentations
Bonding Processes and Analysis in Next Generation Interconnects
　・Paper 6. Fine-Pitch Cu/Polymer Hybrid Bonding using Excimer Laser Damascene Process (Mitsui Chemicals.)
　・Paper 8. Simultaneous Surface Reduction and Self-Passivation via Ar-CH4 Plasma for Cu Hybrid Bonding
(Seoul National University of Science and Technology)
　・Paper 9. Influences of Bonding Misalignment on Copper Bulge Out in Wafer-to-Wafer Hybrid Bonding (Sony)
　・Paper 13. Contamination-Controlled Pre-Assembly for High-Density Die-to-Wafer Hybrid Bonding
(Yokohama National University)
　・Paper 15. Hierarchical 3D-Vertically Multi-Layers Stacking by Transferable Cu/Polymer Hybrid Bonding
(ITRI & National Yang Ming Chiao Tung University)
　・Paper 20. Direct Transfer Bonding of Ultra-Thin Warped Chips for Advanced Heterogeneous 3DIC Integration
with Fine-Pitch Direct/Hybrid Bonding (TAZMO, LINTEC, Tohoku University & Science Tokyo)
　・Paper 24. Impact of Copper Density on Via-to-Via Hybrid Bonding: Morphological and Electrical
Characterizations (CEA-LETI)
　・Paper 26. Exploring Cu-Cu Hybrid Bonding Failure Mechanisms Under Current Stress via 3D Focused Ion Beam
Tomography (State University of New York at Binghamton)
　・Paper 27. An Evaluation of Hybrid Bonding of Cu/SiO2 Using Vacuum Ultraviolet Light Under Redox Gases
(Ushio)
　・Paper 28. Novel O2/H2 Plasma Treatment for Cu Oxide Removal and Dielectric Activation in Hybrid Bonding
(Tokyo Electron)
　・Paper 30. Comprehensive Characterization of Surface Activation for Chip-to-Wafer Hybrid Bonding in 3D Flash
Memory (Tohoku University)
　・Paper 31. High-Throughput Metrology of CMP-treated Surface Topography using Fizeau Interferometry for
Hybrid Bonding (Tohoku University)
　・Paper 32. Interfacial Analysis of Hybrid Bonding Using Water Surface Tension-Driven Self-Assembly for
　 HBM (Tohoku University)

Session 40: Interactive Presentations
Materials, Manufacturing, and Assembly Techniques in Advanced Packaging Solutions
　・Paper 4. Comparative Study of Electroless Noble Metal Layers for Low-Temperature Hybrid Bonding
(Seoul National University of Science and Technology)
　・Paper 5. Metal-Polymer Hybrid Bonding for Contamination Mitigation in Polymer-Based Semiconductor
Packaging (Seoul National University of Science and Technology)
　・Paper 8. Current-Assisted CuCu Bonding at Low Temperature: Process Window and Mechanism
(Hanyang University)
　・Paper 22. High-Performance Low-Temperature SiCN for Hybrid Bonding in Advanced 3D Integration
(Lam Research)
　・Paper 23. Silicon Bridges for Chiplets Heterogeneous Integration with Microbump and Cu-Cu Hybrid Bonding
(Unimicron)

Session 41: Student Interactive Presentations
　・Paper 5. CMPFree and Low-temperature Cu-PI Hybrid Bonding for Rapid Multi-Chip to Wafer Integration
(Fudan University, Jiashan Fudan Research Institute & East China Normal University)
　・Paper 6. Ultrasonic-Assist Thermocompression Al-PI Hybrid Bonding Applied for Chiplet Heterogeneous Bonding
(Fudan University)
　・Paper 7. Robust Design of Hybrid Bonding Considering Cu Pad Inelastic Deformation for Reliability
(Sungkyunkwan University & SK hynix)
　・Paper 10. Enhancing SiO2 Bonding strength with Minimized Cu Surface Oxidation via H2O-assisted Plasma
Treatment (Inha University)
　・Paper 12. Low Temperature and Low Pressure Fine-Pitch Cu-Cu Bonding by Electroplated In-Sn-Passivation
(National Taiwan University)
　・Paper 21. Novel CMP-Free Cu/Polymer Low Temperature Hybrid Bonding with Wide Process Window for
Advanced Packaging and 3D Integration (National Yang Ming Chiao Tung University)
　・Paper 23. High-Resolution Nanoscale X-Ray Imaging for Non-Destructive Inspection of Copper Grains in Fine-
Pitch Pads for Hybrid Bonding
(Rensselaer Polytechnic Institute, IBM, Rensselaer Polytechnic Institute, European,
Synchrotron Radiation Facility)
　・Paper 27. Plasma-Free Wafer-Level Hybrid Bonding Using iCVD Polymer Thin Film for Feasible 3D Multi-Chip
Integration (Dankook University)
　・Paper 36. Novel Immersion-Sn Passivation Process to Address Nanoporous-Cu Seed Layer Etching Challenge for
　　　　　　 Scalable, Low-Temperature, Panel-Level Cu-Cu Bondingv (Georgia Tech and MKS Instruments)

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4．光電融合(Co-PKG) 23件

Session 2: Co-Packaged Optics
　・Paper 1. Proposal of a Novel Opto-Electronic Fan-Out Wafer-Level Packaging Based on Optical RDL and
　　　　　　 Opto-Chiplets (AIST)
　・Paper 2. High-Density, Energy-Efficient CPO Platform with PIC-in-Mold Interposer Architecture for AI/ML Data
Centers (IME)
　・Paper 3. Photonic-Electronic Integration on Glass Substrate with Temperature-Stabilized Vertical Optical
Coupling by Resin-Encapsulated Collimation Mirror
(Sumitomo Electric Industries, FICT & Science Tokyo)
　・Paper 4. Thin-Film Lithium Niobate Hybrid Integration for Co-packaged Optics (UC Davis & Nokia)
　・Paper 5. High-Density Integration of III-V Devices and EICs using Vertical-Coupled Photonic Packages with
Glass-IP and Redistribution Layers (Mitsubishi Electric)
　・Paper 6. A 106-Gb/s × 8-Channel 1060-nm Single-Mode VCSEL-Based Ultra-Compact CPO Transceiver enabling
2-km Parallel-Optical Links (Furukawa Electric, Fujifilm & Science Tokyo)
　・Paper 7. Design and Packaging of a DWDM CW-DFB Laser Array for Co-Integrated Optical Interconnects
(NVIDIA)

Session 8: Die-to-Wafer Hybrid Bonding: Current Advancements and Future Directions
　・Paper 7. Next-Generation Optical-Electrical Co-Design Interconnect Using Low-Temperature Hybrid Bonding
Technology (National Yang Ming Chiao Tung University, Tokyo Electron America, & TOK)
※ ３．ハイブリッド接合でも言及します

Session 15: Optical Interconnects
　・Paper 1. Low-Loss Optical Interconnect Designs in Optimized Glass for Co-Packaged Optics (Corning)
　・Paper 2. Detachable Glass Waveguide Connector for Co‐Packaged Optics on Si Photonics platform with
<1.5 dB/Facet Passive Coupling and 280 mW Power Handling (GF & Corning)
　・Paper 3. Laser Cleaning of Optical Couplers on Photonic Integrated Circuits (Femtum)
　・Paper 4. Development of a High-Efficiency, Wide-Temperature-Range Optical Coupling Structure for CPO
Modules (Kyocera Corporation)
　・Paper 5. High-Density Polymer Waveguide Integration on Glass Substrate for CPO (DNP)
　・Paper 6. Low-Loss Polymer Waveguide Device for Fiber-to-Chip and Chip-to-Chip Connection (Keio University)
　・Paper 7. Integrated Assembly Process For Pluggable Fiber Connector For Co-Packaged Optics (Marvell)

Session 20: Performance Analysis and Metrology of High-Bandwidth Electrical and Optical Interconnects
　・Paper 4. Vertical Interconnects Characterization for 448 Gbps/lane Co-Packaged Optics using Double-Sided
Probing Method (IME)
　・Paper 5. Photonic Interconnects in Glass Core for AI Data Center Applications (Pennsylvania State University)
　・Paper 6. Photonic FabricTM Interconnect for a Scale-up Network Solution in Accelerated Computing (Marvell)
　・Paper 7. Advanced 3D Packaging Optics Engine with Integrated Micro-VCSEL Array for Ultra-High Bandwidth
Optical Interconnect (Rayleigh Vision Intelligence)

Session 25: Optical and Electrical Design for High-Performance Computing
　・Paper 1. Advancing Interconnect Performance and Reliability with Innovations in 3D Photonic Integration
Packaging and Fiber Coupling (Lightmatter)
　・Paper 2. Photonic FabricTM Chiplets for Co-Packaged Optics in AI Data Centers (Marvell)
　・Paper 3. V-groove Based Edge Coupling Enabled by Optical Glass Coupler Attach for Co-packaged Optics (Intel)

Session 33: Emerging Materials and Interconnect Technologies for Advanced Packaging
　・Paper 1. Optical RDL Interposer Technology using Polymeric Hybrid Bonding and Waveguide for Integrated CPO
(Sumitomo Bakelite & Tohoku University)
※ ３．ハイブリッド接合でも言及します